The present invention relates generally to a charge-to-digital converter for use in a charge sensor system.
This invention is related to U.S. Pat. No. 6,366,231, “Integrate and fold analog-to-digital converter with saturation prevention” that describes a Charge-to-Digital (C/D) converter wherein the contents are incorporated by reference herein. That C/D converter performs analog to digital conversion by removing a fixed-size “teaspoon” of charge from the integration capacitor whenever the capacitor (and associated amplifier) get too full (the teaspoon-charge removal is also called a “fold”). The removed charge is discarded so as to allow room for further charge integration, but the removal is tallied. At the end of the integration period, the integer tally is noted and represents the most-significant part of the digital representation of the integrated charge. There is also a remainder charge that was insufficient for another tally. In the pipeline form, or alternatively multistage analog-to-digital converter, this remainder charge is amplified and applied to a second stage of integration, teaspooning (folding), and tallying so as to identify further significant digital bits. The second stage has yet another remainder charge that is then again processed by a third stage, and subsequent charges. The final result is a set of tally results from N (e.g., 4) stages of Integrate and Fold Amplification. The remainder charge in the last stage (of the pipeline) is an insignificant part of the total charge for the initial stage-1 integration period and is ignored.
The present invention relates to the practical aspects of making a pipelined Integrate and Fold based C/D converter that is very linear, has a wide input-charge dynamic range, and will function properly when packed with many other similar C/D converters (e.g., 64) and the associated digital-control logic on the same Integrated-Circuit (IC) die.
To aide in the description of the invention, the Integrate and Fold Amplifier (IFA) stage is cast as either a “current processing” or a “voltage processing” IFA stage (CPIFA or VPIFA, respectively). The current-processing stage is connected to the charge (current) source. The voltage-processing stage processes the residual charge (voltage) from a prior stage. FIG. 1 shows a schematic for the current-process stage and FIG. 2 shows the schematic for that voltage-processing stage. FIG. 3 shows how the two kinds of stages are combined in a pipeline to form a 4-stage C/D converter channel. In FIG. 3, see each stage generates a Fold count (the teaspoon tally) and a residual charge (or representative voltage) as output. The residual charge is passed to the next stage for further processing.
FIG. 1 shows the CPIFA 100 stage with switch positions set for normal integration. Current flows from the sensor 110 through switch Sd 120 into integration (feedback) capacitor Cf1 130. Sensor 110 is typically one of an array of sensors on a common integrated-circuit substrate. Resistor Rd 140 represents the sensor self-leakage resistance, and resistors Ra1 150 through RaK 160 represent the between-sensor leakage resistances to K other sensors. The resistance values are usually very high, but their effect often cannot be ignored. As charge accrues on feedback Cup 130 Cf1, stage-1 output voltage Vout1 170 becomes proportionally more negative. With positive current, Vout1 170 eventually becomes more negative than threshold voltage Vth1 180 so that comparator 190 trips and requests a “fold” from the Fold Processor 210 in the Digital Control bloc 200. When appropriate, the Fold Processor 210 responds with an accurately timed fold pulse that switches fold switch 220 thus removing Fold Current Ifold1 230 from the integration capacitor for the pulse duration. Over an integration period, multiple fold requests and folds may occur and the number of folds is counted for that integration period. At the end of the integration period, after all folding is completed, a residual charge remains on integration capacitor 130 and it is proportionally represented by Vout1 170 at the Analog Residual output 240. This voltage can be processed by the voltage-processing IFA stage 200 of FIG. 2 (or by conventional analog-to-digital conversion means) to extract more digital resolution of the total integrated charge.
At the end of each integration period, after the Analog Residual output 240 has been sampled by a following stage (not shown) or by an A/D converter (not shown), the stage-1 IFA can be reset so that the Analog Residual value starts at zero for each integration period. This is the “resetting mode” of CPIFA operation. Alternatively, this reset can be eliminated, but then the stage-1 Fold Count and the change in stage-1 Analog Residual together indicate the total integrated charge. This is the “no-resetting” mode of CPIFA operation.
Referring further to FIG. 1, in the resetting mode, before each integration period begins, reset switch Sr1 250 is closed and auto-zero switch Saz1 260 is connected to ground. This eliminates the prior residual charge from integration capacitor Cf1 130 and samples the small but typically non-zero input-offset voltage of imperfect amplifier A1 270 onto Cf1 130 and onto the parasitic sensor and interconnection capacitance, Cd 280. This makes the stage-1 analog residual value be zero when the total input charge is zero. During the reset period, current is not integrated by Cf1 130 and any charge source during this time is wasted. It is advantageous to minimize wasted charge source.
In the no-resetting mode, current is continually integrated. Charge is not wasted. Also, reset switch 250 is not closed and auto-zero switch 260 is not connected to ground. This has the advantage that inherent noise from amplifier 270 is not sampled onto Cf1 130 and Cd 280 as is done at the end of the reset period in the resetting mode of operation. It is advantageous to reduce any noise contributed to the integrated charge.
FIG. 2 shows the voltage-processing IFA (VPIFA) stage 300. In practice, the Input Voltage node is connected directly to the Analog Residual node (240-FIG. 1) of a preceding CPIFA or VPIFA stage (but it can also be connected directly to a voltage that is to be measured, not necessarily from a sensor). The VPIFA operates by first sampling the input voltage onto sample capacitor Cs2 310 as a stored charge, and then measuring the stored charge in a manner similar to the way a CPIFA measures integrated current. The sampling process consists of setting auto-zero switch Saz2 320 to ground, closing reset switch Sr2 330, and closing sample switch 340. During this time, discharge switch Sdis2 350, bypass switch Sbyp2 360 and fold switch Sf2 370 are all open. This samples the amplifier input-offset voltage onto Cf2 380, and the input voltage (minus the input-offset voltage) onto Cs2 310. This sampling method reduces/eliminates the effect of a non-zero amplifier input-offset voltage.
After sampling, the charge stored on sample capacitor Cs2 310 is measured by opening reset switch Sr2 330, setting auto-zero switch Saz2 320 to the downward position, and closing discharge switch Sdis2 350. Charge then flows from Cs2 310 to Cf2 380, and Vout2 390 goes more negative. If there is sufficient sampled charge, comparator Comp2 400 eventually trips and requests a fold. The Fold Processor 410 then generates a fold pulse and Vout2 390 is taken more positive. This is similar to operation of the CPIFA 100 (FIG. 1).
FIG. 3 shows a pipeline consisting of 3 VPIFA stages 300 following a CPIFA 100. Each stage emits a fold count associated with the input charge, and the size of a fold in each stage must be determined (calibrated) in order to determine the stage-1 input-referred charge value associated with the set of fold counts. For linear operation, the fold sizes must not change in an unknown manner between fold-size calibrations. Therefore, it is advantageous to have an IFA-based C/D converter whose fold-sizes are independent of the signal levels in the pipeline.
The sampling process between pipeline stages must be very accurate if high linearity is to be achieved. (Therefore, it's advantageous to have an IFA-based C/D converter with very high sampling accuracy between stages.)
Finally, multiple C/D converter channels (not shown) may be included on the same integrated circuit (IC) along with the associated digital control logic. Digital circuits and analog-switch commands both produce digital noise. Therefore, it is advantageous for a wide-range C/D converter (one that operates at very small signal levels) to be made insensitive to any digital noise and/or be able to ignore noise that occurs at predictable times.
In FIG. 1, the sensor leakage resistances Ra 140 are not infinite, and the amplifier input-offset voltage 290 is not zero. This means that there will be a leakage-current contribution to the input current, and the sign and magnitude of the leakage will depend on the relative signs and magnitudes of the input voltages of the CPIFA of the different channels. If the input voltage of one channel were to go very far positive or negative, that channel would corrupt the integration results for other channels by adding substantial inter-channel leakage via resistors Ra1 150 through RaK 160. Therefore, it is advantageous to insure that the input of each channel will remain near zero volts under all input conditions (for example, even when the CPIFA is overloaded or saturated by an input current that is too large).
What is needed is multi-channel analog to digital conversion circuit that overcomes the challenges described above. Some aspects apply only to a pipelined IFA channel (more than one stage) while others apply only to the current-processing IFA stage.